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Freescale Semiconductor /MK21D5WS /PDB0 /CH1DLY1

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Interpret as CH1DLY1

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0DLY0RESERVED

Description

Channel n Delay 1 Register

Fields

DLY

PDB Channel Delay
RESERVED

no description available

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data